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april 2008 rev 2 1/29 29 ST6G3240 dual supply level translator for dual memory cards (mini sd/micro sd + managed nand) features high speed: t pd (a to b) = 5 ns at t a = 85 c with v cca = 1.8 v, v ccbn = 3.0 v low power dissipation: i cca = i ccbn = 5 a (max.) at t a =85 c balanced propagation delays: t plh t phl operating voltage range: ?v cca (opr) = 1.4 to 3.6 v ?v ccbn (opr) = 1.4 to 3.6 v b-side power supplies (v ccb1 and v ccb2 ) can be different and separately controlled interchangeable voltage levels: v cca can either be greater than or less than v ccbn low power mode: when v ccbn is grounded or floating, there is very low quiescent current on v cca power down detection: when either one of the b-side power supplies (v ccb1 and v ccb2 ) is grounded or floating, the corresponding port-n goes into high-z state automatically latch-up performance exceeds 500 ma (jesd17) esd protection: 2 kv hbm integrated pull-up resistor and level translator on the ms_insert pin integrated pull-up resistor for card-detect pin description the ST6G3240 is a dual supply low voltage cmos level translator supporting the dual function of mini sd/micro sd card and managed nand memories. it is designed for use as an interface between three systems using 3.3, 2.5 and 1.8 v respectively. the ST6G3240 is capable of achieving high speed operation and at the same time maintaining low power dissipation. while the a port is designed to track v cca , the bn port (ncmd, ndat, nclk) is designed to track v ccbn . the device is intended for a two-way asynchronous communication between data buses. tfbga 36 table 1. device summary order code package packing ST6G3240tbr tfbga36 (3.6 x 3.6 mm) tape and reel www.st.com
contents ST6G3240 2/29 contents 1 ST6G3240 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ST6G3240 ST6G3240 general description 3/29 1 ST6G3240 general description the ST6G3240 is a dual supply low voltage cmos level translator supporting the dual function of mini sd/micro sd card and managed nand memories. it is designed for use as an interface between three systems using 3.3, 2.5 and 1.8 v respectively. the ST6G3240 is capable of achieving high speed operation and at the same time maintaining low power dissipation. while the a port is designed to track v cca , the bn port (ncmd, ndat, nclk) is designed to track v ccbn . the device is intended for a two-way asynchronous communication between data buses. the direction of data transmission is determ ined by cmd-dir/data0-dir/dat123-dir inputs. in the typical application the bn-port interfaces with the 3 v bus and the a-port with the 1.8v bus. with interchangeable voltage levels, there is no restriction on the voltage settings for each supply. v cca can be less than or greater than v ccb1 or v ccb2 . for example, v cca = 2.5 v, v ccb1 = 3.6 v, v ccb2 = 1.8 v. full low power mode this device can be entered into 'full lower power mode' by setting all the inn pins to low or high, which will disable the device completely. partial low power mode alternatively, the device can be set into 'partial low power mode' by grounding or floating one of the v ccbn power supplies. this will set all the corr esponding output po rt-n to high-z. however, it is important to note that v cca power supply must not be grounded or floating whenever v ccbn is connected to a power supply as th is will lead to significant current consumption increase.
pin settings ST6G3240 4/29 2 pin settings 2.1 pin connection figure 1. pin connection (top through view) note: it is required that v cc supply and ground pins are in close proximity, so as to allow for easy capacitive coupling in application. table 2. pin mapping 123456 a vcca gnd in1 cd gnd vccb1 b cmd.h cmd-dir in2 1cmd 1dat0 2dat0 c dat0.h dat0-dir gnd 2cmd 1dat1 2dat1 d dat1.h dat123-dir gnd gnd 1dat2 2dat2 e dat2.h clk-f 2clk 1clk 1dat3 2dat3 f dat3.h clk-h ms_insert ms_insertb 1 gnd vccb2 12345 6 a b c d e f tfbga36
ST6G3240 pin settings 5/29 2.2 pin description table 3. pin description pin type side symbol name and function a1 - a v cca a-side power supply a2 - - gnd ground (0 v) a3 i a in1 output enable pin. functions together with in2 pin. refer to truth table for more information on the settings a4 - a cd card detect pin with 100 k internal pull- up resistor on the a-side a5 - - gnd ground (0 v) a6 - b1 v ccb1 b1-side power supply b1 i/o a cmd.h command pin for a-side b2 i a cmd-dir command direction pin high => cmd.h input, ncmd output low => cmd.h output, ncmd input b3 i a in2 output enable pin. functions together with in1 pin. refer to truth table for more information on the settings b4 i/o b1 1cmd command pin for b1-side b5 i/o b1 1dat0 data0 pin for b1-side b6 i/o b2 2dat0 data0 pin for b2-side c1 i/o a dat0.h data0 pin for a-side c2 i a dat0-dir data direction pin for dat0 high => dat0.h input, ndat0 output low => dat0.h output, ndat0 input c3 - - gnd ground (0 v) c4 i/o b2 2cmd command pin for b2-side c5 i/o b1 1dat1 data1 pin for b1-side c6 i/o b2 2dat1 data1 pin for b2-side d1 i/o a dat1.h data1 pin for a-side d2 i a dat123-dir data direction pin for dat1-dat3 high => dat123.h input, ndat123 output low => dat123.h output, ndat123 input d3 - - gnd ground (0 v) d4 - gnd ground (0 v) d5 i/o b1 1dat2 data2 pin for b1-side
pin settings ST6G3240 6/29 cmd command pin is a bidirectional line. the host and card drivers are operating in push-pull configuration. dat0-3 all data lines are bi-directional lines. host and card drivers operate in push-pull mode. clk clock is a host to card signal . clk operates in push-pull mode. feedback (return) clock is a feedback clock signal from level shifter to the host for controlling delays. cd card detect with internal pull up resistor. pin will be pulled to v cca when it is in high state. in1, in2 selection pins. when in1 and in2 are set to disa bled state, all the data bus will be in high- impedance. when enabled, a ll the data bus will be working as a level translator between port a and port bn (refer to the truth table for possible pin configuration). pin type side symbol name and function d6 i/o b2 2dat2 data2 pin for b2-side e1 i/o a dat2.h data2 pin for a-side e2 o a clk-f feedback clock pin on a-side e3 o b2 2clk clock output pin for b2-side e4 o b1 1clk clock output pin for b1-side e5 i/o b1 1dat3 data3 pin for b1-side e6 i/o b2 2dat3 data3 pin for b2-side f1 i/o a dat3.h data3 pin for a-side f2 i a clk.h clock input pin for a-side f3 - a ms_insert ms_insert pin with 100 k internal pull- up resistor on a-side f4 o b1 ms_insertb1 ms_insert pin on b1-side f5 - - gnd ground (0v) f6 - b2 v ccb2 b2-side power supply table 3. pin description (continued)
ST6G3240 logic diagram 7/29 3 logic diagram figure 2. ST6G3240 logic block diagram v ccb1 dat12 3 - dir dat1.h dat2.h dat 3 .h clk.h clk - f data0-dir dat0.h cmd.h gnd 1c l k 2d a t 0 1d a t 1 1d a t 2 1d a t 3 1c m d in1 cd 100k 3 2c m d in2 m s _ in s ertb1 v ccb2 m s _ in s ert v ccb1 100k s 00091
logic diagram ST6G3240 8/29 figure 3. input and output equivalent circuit h - z: high impedance table 4. truth table in1 in2 cmd-dir cmd.h dat0-dir dat0.h dat123- dir dat1.h dat2.h dat3.h clk.h clk-f.h 1cmd 1dat0 1dat1 1dat2 1dat3 1clk 2cmd 2dat0 2dat1 2dat2 2dat3 2clk h h h-z h-z h-z h-z h-z h-z l h active active active active active h-z h l active active active active h-z active l l h-z h-z h-z h-z h-z h-z table 5. ms_insert truth table ms_insert (referenced to v cca ) ms_insertb1 (referenced to v ccb1 ) hh ll
ST6G3240 maximum rating 9/29 4 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 6. absolute maximum ratings symbol parameter value unit v cca supply voltage -0.5 to 4.6 v v ccb1 supply voltage -0.5 to 4.6 v v ccb2 supply voltage -0.5 to 4.6 v v i dc input voltage -0.5 to 4.6 v v i/oa dc i/o voltage (output disabled) -0.5 to 4.6 v v i/obn dc i/o voltage (output disabled) -0.5 to 4.6 v v oa dc output voltage -0.5 to v cca +0.5 v v obn dc output voltage -0.5 to v ccbn +0.5 v i ik dc input diode current - 20 ma i ok dc output diode current - 50 ma i oa dc output current 50 ma i obn dc output current 50 ma i cca dc v cca or ground current 100 ma i ccbn dc v ccbn or ground current 100 ma p d power dissipation at t a =70oc (1) 1. derate above 70oc by 18.5 mw/c 400 mw t stg storage temperature -65 to 150 c t l lead temperature (10 sec) 260 c table 7. recommended operating conditions symbol parameter value unit v cca supply voltage 1.4 to 3.6 v v ccb1 supply voltage 1.4 to 3.6 v v ccb2 supply voltage 1.4 to 3.6 v v i input voltage (/in1, /in2, cmd-dir, dat0-dir, dat123-dir) 0 to v cca v v i/oa i/o voltage 0 to v cca v v i/obn i/o voltage 0 to v ccbn v
maximum rating ST6G3240 10/29 symbol parameter value unit t op operating temperature -40 to 85 c dt/dv input rise and fall time 0 to 10 ns/v table 7. recommended operating conditions (continued)
ST6G3240 electrical characteristics 11/29 5 electrical characteristics table 8. dc specifications for v cca symbol parameter test conditions value unit v cca (v) v ccb (v) t a = 25 c -40 to 85 c min max min max v ih high level input voltage 1.4 ? 1.95 1.4 ? 3.6 0.65 v cca 0.65 v cca v 1.95 ? 2.7 1.7 1.7 2.7 ? 3.6 2.0 2.0 v il low level input voltage 1.4 ? 1.95 1.4 ? 3.6 0.35 v cca 0.35 v cca v 1.95 ? 2.7 0.7 0.7 2.7 ? 3.6 0.8 0.8 v oh high level output voltage 1.4 ? 3.6 1.4 ? 3.6 i oh = -100 a v cca -0.1 v cca -0.1 v 1.4 i oh = -1 ma 1.20 1.20 1.65 i oh = -2 ma 1.40 1.40 2.7 i oh = -4 ma 2.30 2.30 3i oh = -8 ma 2.45 2.45 3.6 i oh = -8 ma 3.05 3.05 v ol low level output voltage 1.4 ? 3.6 1.4 ? 3.6 i ol = 100a 0.10 0.10 v 1.4 i ol = 1 ma 0.20 0.20 1.65 i ol = 2 ma 0.25 0.25 2.7 i ol = 4 ma 0.40 0.40 3i ol = 8 ma 0.55 0.55 3.6 i ol = 8 ma 0.55 0.55 i ia input leakage current per input channel 1.4 ? 3.6 1.4 ? 3.6 v ia =v cca or gnd 0.5 5 a i dir input leakage current per control input (dir) 1.4 ? 3.6 1.4 ? 3.6 v dir = v cca or gnd 0.1 2 a
electrical characteristics ST6G3240 12/29 1 all a-ports i/os and control inputs are powered by v cca . 2 all bn-ports i/os are powered by v ccbn . 3 there is no restriction on v cca or v ccbn , either one can be greater than the other. symbol parameter test conditions value unit v cca (v) v ccb (v) t a = 25 c -40 to 85 c min max min max i oza high impedance output leakage current 1.4-3.6 1.4 ? 3.6 v ia = gnd to 3.6 v vibn = gnd to 3.6 v in1, in2 = v cca or in1, in2 = gnd 1.0 10 a i off power off a-side i/o leakage current 00 v ia = 0 to 3.6 v inn = 0, dir=0 1.0 10 a i cd cd pin input leakage current 3.6 1.4 ? 3.6 v cd = 0 50 500 a i ms ms pin input leakage current 3.6 1.4 ? 3.6 v ms = 0 50 500 a table 8. dc specifications for v cca (continued)
ST6G3240 electrical characteristics 13/29 table 9. dc specification for v ccbn symbol parameter test conditions value unit v cca (v) v ccbn (v) t a = 25 c -40 to 85 c min max min max v ih high level input voltage 1.4 ? 3.6 1.4 ? 1.95 0.65 v ccbn 0.65 v ccbn v 1.95 ? 2.7 1.7 1.7 2.7 ? 3.6 2.0 2.0 v il low level input voltage 1.4 ? 3.6 1.4 ? 1.95 0.35 v ccbn 0.35 v ccbn v 1.95 ? 2.7 0.7 0.7 2.7 ? 3.6 0.8 0.8 v oh high level output voltage 1.4 ? 3.6 1.4 ? 3.6 i oh = -100 a v ccbn - 0.1 v ccbn - 0.1 v 1.4 i oh = -1 ma 1.10 1.10 1.65 i oh = -2 ma 1.20 1.20 2.7 i oh = -4 ma 2.20 2.20 3.0 i oh = -8 ma 2.30 2.30 3.6 i oh = -8 ma 3.00 3.00 v ol low level output voltage 1.4 ? 3.6 1.4 ? 3.6 i ol = 100 a 0.20 0.20 v 1.4 i ol = 1 ma 0.35 0.35 1.65 i ol = 2 ma 0.45 0.45 2.7 i ol = 4 ma 0.55 0.55 3.0 i ol = 8 ma 0.70 0.70 3.6 i ol = 8 ma 0.70 0.70 i ibn input leakage current per input channel 1.4 ? 3.6 1.4 ? 3.6 v ibn =v ccbn or gnd 0.5 5 a i ozbn high impedance output leakage current 3.6 3.6 v ia = gnd to 3.6 v v ibn = gnd to 3.6 in1,in2 = v cca or in1,in2 = gnd 1.0 10 a i off power off b- side i/o leakage current 00 v ibn =0 to 3.6v inn= 0, dir =0 1.0 10 a
electrical characteristics ST6G3240 14/29 table 10. dc quiescent current symbol parameter test conditions value unit v cca (v) v ccb1 (v) v ccb2 (v) t a = 25 c -40 to 85 c min max min max i cca quiescent supply current for a-side 1.4 ? 3.6 1.4 ? 3.6 1.4 ? 3.6 v ia =v cca or gnd v ibn =v ccbn or gnd v cd =v ms =v cca 15 a 1.4 ? 3.6 0 1.4 ? 3.6 1 5 1.4 ? 3.6 1.4-3.6 0 1 5 1.4 ? 3.6 0 0 1 5 i ccbn quiescent supply current for bn-side 1.4 ? 3.6 1.4 ? 3.6 1.4 ? 3.6 v ia =v cca or gnd v ibn =v ccbn or gnd v cd =v ms =v cca 15 a i ccaz high impedence quiescent supply current for a- side 1.4 ? 3.6 1.4 ? 3.6 1.4 ? 3.6 in1 = gnd/v cca in2 = gnd/v cca 0.2 1 a 1.4 ? 3.6 1.4 ? 3.6 1.4 ? 3.6 in1 = v cca and in2 = gnd 0.5 2 1.4 ? 3.6 1.4 ? 3.6 1.4 ? 3.6 in1 = gnd and in2 = v cca 0.5 2
ST6G3240 electrical characteristics 15/29 table 11. ac electrical characteristics (f = 10 mhz, 50% duty cycle (1) ) v cca = 1.5 v 0.1 v paramete r from (input) to (output) v ccbn =1.8 v 0.15 v v ccbn =2.5 v 0.2 v v ccbn =3.0 0.3 v v ccbn =3.3 v 0.3 v unit min max min max min max min max t plhab, t phlab propagation delay time from a to b (c l = 15 pf, r l =2k ? ) cmd.h ncmd 9 6 5.5 5.5 ns clk.h nclk 9 6 5.5 5.5 clk.h clk-f 18 12 11 11 datx.h ndatx 9 6 5.5 5.5 t plhba, t phlba propagation delay time from b to a (c l =7pf, r l =2k ? ) ncmdcmd.h9999 ns ndatxdatx.h9999 t pzl, t pzh output enable time (c l =7 pf, r l =2k ? ) inn a 22 22 22 22 ns output enable time (c l =15pf, r l =2k ? ) innbn 22222222 t plz, t phz output disable time (c l =7 pf, r l =2k ? ) inn a 33 33 33 33 ns output disable time (c l =15pf, r l =2k ? ) innbn 33333333 t dir, enable dira 8888 ns dirb 9999 t dir, disable dira 7777 ns dirb 8888 t oslh, t os hl output to output skew time (2) 1111ns t cdlh, t cd hl clock and data skew time 1111ns f max clock abn 52525252 mhz bna 52525252 data a bn 104 104 104 104 mbps bn a 104 104 104 104 1. refer to figure 4. 2. skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either high or low ( t oslh = | t plhm - t plhn |, t oshl = | t phlm ? t phln | )
electrical characteristics ST6G3240 16/29 table 12. v cca = 1.8 v 0.15 v parameter from (input) to (output) v ccbn =1.8 v 0.15 v v ccbn =2.5v 0.2v v ccbn =3.0 0.3 v v ccbn =3.3 v 0.3v unit min max min max min max min max t plhab, t phlab propagation delay time from a to b (c l =15pf, r l =2k ? ) cmd.h ncmd 8.5 5.5 5 5 ns clk.h nclk 8.5 5.5 5 5 clk.h clk-f 17 11 10 10 datx.h ndatx 8.5 5.5 5 5 t plhba, t phlba propagation delay time from b to a ( c l =7 pf, r l =2k ? ) ncmdcmd.h7777 ns n dat x dat x . h 7 7 7 7 t pzl, t pzh output enable time ( c l =7pf, r l =2 k ? ) inn a 15 15 15 15 ns output enable time (c l =15pf, r l =2 k ? ) innbn 15151515 t plz, t phz output disable time ( c l =7pf, r l =2k ? ) inn a 22 22 22 22 ns output disable time (c l =15pf, r l =2k ? ) innbn 22222222 t dir, enable dira 7777 ns dirb 8888 t dir, disable dira 5555 ns dirb 6666 t oslh, t osh l output to output skew time (1) 1111ns t cdlh, t cdh l clock and data skew time 1111ns f max clock abn 52525252 mhz bna 52525252 data a bn 104 104 104 104 mbp s bn a 104 104 104 104 1. skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either high or low ( t oslh = | t plhm - t plhn |, t oshl = | t phlm ? t phln | )
ST6G3240 electrical characteristics 17/29 table 13. v cca = 2.5 0.2 v parameter from (input) to (output) v ccbn =1.8v 0.15v v ccbn =2.5v 0.2v v ccbn =3.0 0.3v v ccbn =3.3v 0.3v unit min max min max min max min max t plhab, t phlab propagation delay time from a to b ( c l =15pf, r l = 2 k ) cmd.h ncmd 7.5 5 4.5 4.5 ns clk.h nclk 7.5 5 4.5 4.5 clk.h clk-f 15 10 9 9 datx.h ndatx 7.5 5 4.5 4.5 t plhba, t phlba propagation delay time from b to a (c l =7pf, r l =2k ? ) ncmdcmd.h5555 ns n dat x dat x . h 5 5 5 5 t pzl, t pzh output enable time (c l =7pf, r l =2k ? ) inn a 11 11 11 11 ns output enable time (c l =15 pf, r l =2k ? ) innbn 11111111 t plz, t phz output disable time (c l =7 pf, r l =2 k ? ) inn a 21 21 21 21 ns output disable time (c l =15pf, r l =2 k ? ) innbn 21212121ns t dir, enable dira 5555 ns dirb 6666 t dir, disable dira 5555 ns dirb 6666 t oslh, t oshl output to output skew time (1) 1111ns t cdlh, t cdhl clock and data skew time 1111ns f max clock abn 52525252 mhz bna 52525252 data a bn 104 104 104 104 mbps bn a 104 104 104 104 1. skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either high or low ( t oslh = | t plhm - t plhn |, t oshl = | t phlm ? t phln | )
electrical characteristics ST6G3240 18/29 table 14. v cca = 3.3 v 0.3 v parameter from to v ccbn = 1.8 v 0.15 v v ccbn = 2.5 v 0.2 v v ccbn = 3.0 0.3 v v ccbn = 3.3 v 0.3 v unit minmaxminmaxminmaxminmax t plhab, t phlab propagation delay time from a to b (c l =15pf, r l =2k ? ) cmd.h ncmd 7 4.5 4.3 4.3 ns clk.h nclk 7 4.5 4.3 4.3 clk.h clk-f 14 9 8.6 8.6 datx.h ndatx 7 4.5 4.3 4.3 t plhba, t phlba propagation delay time from b to a (c l =7pf, r l =2k ? ) ncmdcmd.h4444 ns ndatxdatx.h4444 t pzl, t pzh output enable time (c l =7pf, r l =2k ? ) inna 9999 ns output enable time (c l =15pf, r l =2k ? ) innbn9999 t plz, t phz output disable time (c l =7pf, r l =2 k ? ) inn a 20 20 20 20 ns output disable time ( c l =15pf, r l =2 k ? ) innbn 20202020 t dir, enable dira 4444 ns dirb 5555 t dir, disable dira 4444 ns dirb 5555 t oslh, t osh l output to output skew time (1) 1111ns t cdlh, t cdh l clock and data skew time 1111ns f max clock abn 52525252 mhz bna 52525252 data a bn 104 104 104 104 mbp s bn a 104 104 104 104 1. skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either high or low ( t oslh = | t plhm - t plhn |, t oshl = | t phlm ? t phln | )
ST6G3240 electrical characteristics 19/29 table 15. output slew rate (f = 1 mhz, 50% duty cycle, c l =15 pf on bn-side; c l =7 pf on a-side) symbol parameter from to test condition t a = -40 to 85 c unit v cca = 1.8 v 0.15v v ccbn = 3.0 v 0.3v min max t r rise time 10% 90% 3.5 ns t f fall time 10% 90% 3.5 ns table 16. capacitance characteristics symbol parameter test condition value unit v cca (v) v ccbn (v) t a = 25 c -40 to 85 c min typ max min max c inbn input capacitance open open 9 pf c i/oa input/output capacitance for a-side 1.8 3.0 f=1mhz v bias = 250 mv v pp =500mv 5pf c i/obn input/output capacitance for bn-side 1.8 3.0 f=1mhz v bias =250mv v pp =500mv 11 pf c pd power dissipation capacitance 2.5 3.3 f=10mhz 29 pf 1.8 3.3 29
test circuit ST6G3240 20/29 6 test circuit figure 4. test circuit r t is the z out of the pulse generator, typically 50 ? . table 17. test circuit switches test c l (pf) r l /r 1 (k ) switch a-side b-side t plh , t phl 7 15 2 open t pzl , t plz 715 2 2v cc t pzh , t phz 715 2 gnd table 18. waveform symbol value symbol v cc 3.0 to 3.6 v 2.3 to 2.7 v 1.65 to 1.95 v v ih v cc v cc v cc v m 1.5 v v cc /2 v cc /2 v x v ol + 0.3 v v ol + 0.15 v v ol + 0.15 v v y v oh - 0.3 v v oh - 0.15 v v oh - 0.15 v
ST6G3240 test circuit 21/29 figure 5. waveform - propagation delay (f = 1 mhz, 50% duty cycle) figure 6. waveform - output enable/disable (f = 1 mhz, 50% duty cycle) in 1, in2
test circuit ST6G3240 22/29 figure 7. application block diagram 10 6 6 dat0 dat1 dat2 dat3 dat0 dir dat123 dir cmd cmd dir clk clk-f in1 in2 2dat0 2dat1 2dat2 2dat3 2cmd 2clk 10 01 1dat0 1dat1 1dat2 1dat3 1cmd 1clk cd r r . . . ms_insert ms_insert (1) ST6G3240 r combocard holder ( mi crosd + m2 ) vcca vccb2 vccb1 card detection external switch 100k ? v cca cd base band 100k ?
ST6G3240 package mechanical data 23/29 7 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com . figure 8. tfbga package outline
package mechanical data ST6G3240 24/29 figure 9. recommended footprint table 19. tfbga 36 mechanical data symbol millimeters min typ max a11.11.16 a1 0.25 a2 0.78 0.86 b 0.25 0.30 0.35 d 3.50 3.60 3.70 d1 2.50 e 3.50 3.60 3.70 e1 2.50 e0.50 f0.55
ST6G3240 package mechanical data 25/29 figure 10. carrier tape information
package mechanical data ST6G3240 26/29 figure 11. reel dimensions table 20. reel dimensions tape width n w1 w2 max c 12 178 5 mm 12.4 (+2,-0) 18.4 13 0.25
ST6G3240 package mechanical data 27/29 figure 12. reel information
revision history ST6G3240 28/29 8 revision history table 21. document revision history date revision changes 27-mar-2008 1 initial release. 18-apr-2008 2 minor text changes. modified f max values in ta bl e 1 1 , ta b l e 1 2 , ta b l e 1 3 and ta b l e 1 4 .
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